`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:45:05 08/28/2012
// Design Name:   timer
// Module Name:   C:/Users/maye/Desktop/alle archivos/lab2/timer_prueba.v
// Project Name:  lab2
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: timer
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module timer_prueba;

	// Inputs
	reg [3:0] value;
	reg start_timer;
	reg clk_i;
	reg reset;
	reg divisor;

	// Outputs
	wire expired;

	// Instantiate the Unit Under Test (UUT)
	timer uut (
		.value(value), 
		.start_timer(start_timer), 
		.clk_i(clk_i), 
		.expired(expired), 
		.reset(reset),
		.divisor(divisor)
	);

	always begin 
		#20 clk_i=~clk_i;
	end
	
	always begin 
		#50 divisor=~divisor;
	end
	initial begin
		// Initialize Inputs
		value = 6;
		start_timer = 1;
		clk_i = 0;
		reset = 0; 
		divisor = 0;

		// Wait 100 ns for global reset to finish
		#1000;
      value=2;  
		// Add stimulus here

	end
      
endmodule

